1. Field of the Invention
The present invention generally relates to a radio communication apparatus which receives a digital modulation signal. More particularly, this invention pertains to an apparatus and a method for demodulating a received digital modulation signal.
2. Description of the Related Art
GMSK (Gaussian filtered Minimum Shift Keying), which is known as one of narrow-band digital modulation systems, is used in mobile communications involving a mobile radiophone or a portable radiophone, for example. This radio communication apparatus for mobile communications performs frequency detection to demodulate a received GMSK modulation signal to a digital signal of a base band, periodically samples the voltage level of the detection signal, and identifies data according to each sampled level. In identifying data, the sampled level is compared with two threshold voltages L1 and L2 for data discrimination. When the sampled level is higher than the voltage L1, the data is discriminated to be "1" while when the former is lower than the voltage L2, the data is judged to be "0".
The above-described radio communication apparatus is generally equipped with a digital PLL circuit to reproduce a clock necessary to sample the detection signal. In this case, this apparatus detects a zero cross where the frequency detection signal crosses the zero level in accordance with a change in data, and generates a zero-cross signal to trigger the PLL circuit at each zero cross point. When the zero-cross signal triggers the PLL circuit, the PLL circuit controls the phase of the zero-cross signal which is generated in accordance with the data rate frequency in the radio communication apparatus, and reproduces a clock synchronous with the detection signal.
When the frequency detection signal is distorted or noise is increased due to deterioration of the receiving conditions, zero crossing frequently occurs in other points than actual data-altering points. If the PLL circuit is triggered in association with every zero cross, the clock used for sampling the detection signal will not correctly be reproduced.
Published Unexamined Japanese Patent Application No. Hei 1-240024 discloses the art for preparing a predicting time slot signal to predict the next zero-cross point based on the reproduced clock, and controlling the phase of the reproduced clock at the zero-cross point only when a zero cross occurs within the time slot.
FIG. 1 illustrates a clock reproducing circuit disclosed in this prior art. A GMSK modulation signal is received by an antenna 1, and is in turn detected by a frequency detector 2. A detection signal, the output from the detector 2, is supplied to a zero-cross selector 3. The zero-cross selector 3 includes a comparator 11, an exclusive OR (EX-OR) gate 12, an AND gate 13, a D type flip-flop 14, an RS flip-flop 15 and an inverter 16, as shown in FIG. 2. The zero-cross selector 3 detects each zero cross of the detection signal, and generates a zero-cross signal corresponding only to the zero cross, which has been detected while a time slot signal is supplied from a time slot signal generator 4. Based on a reproduced clock signal to be described later, the time slot signal generator 4 predicts the zero cross of the next detection signal, and generates the time slot signal during a predetermined period of time including a timing to be predicted as shown in FIG. 3. A high stable fixed oscillator 9 generates a pulse at a frequency N times as high as the data rate frequency of a digital signal, and supplies the pulse as a clock signal to a phase controller 8. The phase controller 8 controls the phase of the clock signal, and sends that signal to a frequency divider 5. The frequency divider 5 frequency-divides the clock signal into the data rate frequency, and generates a reproduced clock signal. A phase comparator 6 compares the phase of the zero-cross signal from the zero-cross selector 3 with that of the reproduced clock signal from the frequency divider 5, and supplies a phase difference signal corresponding to the resultant phase difference to a sequential filter 7. Based on the phase difference signal, the sequential filter 7 supplies a lead signal to the phase controller 8 when the reproduced clock signal lags behind the zero-cross signal, while sending a lag signal to the controller 8 when the reproduced clock signal leads the zero-cross signal. In response to the lag signal, the phase controller 8 eliminates part of a train of the pulses included in the clock signal to be sent from the high stable fixed oscillator 9. When receiving the lead signal, the phase controller 8 adds a pulse to the pulse train included in the clock signal. The phase of the reproduced clock signal lags when the frequency divider 5 frequency-divides the clock signal with part of the pulse train eliminated, while it leads when the divider 5 frequency-divides the clock signal with some pulse added to the pulse train. The reproduced clock signal is always controlled as described above, to be synchronized with the detection signal.
Published Unexamined Japanese Utility Model Application No. Hei 2-8243 discloses the art of compensating for the center level of a detection signal before identifying data. FIG. 4 illustrates a level compensator disclosed in this document. The compensator comprises an antenna 21, a frequency detector 22, a subtractor 23, a data discriminating circuit 24 and a level detector 25. A GMSK modulation signal, received at the antenna 21, is detected by the detector 22. The detector 22 generates a detection signal to be supplied through the subtractor 23 to the data discriminating circuit 24 and the level detector 25. This detection signal is represented in the form of an eye pattern in FIG. 5. "VR" represents a reference voltage, "V1" and "V2" are first and second decision levels, "Vs" is a signal amplitude, and "V(i-2)", "V(i-1)", "V(i)", "V(i+1)" and "V(i+2)" are signal voltage levels corresponding to a series of data. The level detector 25 includes an A/D converter 26, a clock reproducing circuit 27, an error signal generator 28, an integrator 29 and a D/A converter 30. The A/D converter 26 shifts the voltage level of the detection signal by the reference voltage VR and performs A/D conversion on the sifted level of the detection signal, which is in turn supplied to the error signal generator 28. The error signal generator 28 compares the level of the voltage undergone the A/D conversion, for example, V(i), with those of the threshold voltages V1 and V2 for phase detection. The error signal generator 28 determines the following augmenters: V(i)-Vs when V(i)&gt;V1, V(i) when V2&lt;V(i)&lt;V1, and V(i)+Vs when V(i)&lt;V2. The individual augmenter corresponds to the drift from the center frequency level of the detection signal. The error signal generator 28 generates a signal of the reference voltage VR subtracted from the augmenter, as an error signal. The integrator 29 integrates the error signal, on which the D/A converter 30 then performs D/A conversion. The subtractor 23 subtracts the output signal from the D/A converter from the detection signal, to set the center level of the detection signal exactly to "zero." The data discriminating circuit 24 discriminates data based on the detection signal acquired in this manner.
The clock reproducing circuit shown in FIG. 1, however, malfunctions when noise is superposed on the detection signal within a predicted period of time that a time slot signal indicates. Should noise a be superposed on the detection signal as shown in FIG. 6, the timing at which the output of the AND gate 13 should rise would be shifted to time t' from the normal rising time t.
Further, when the frequency of a GMSK modulation signal is detected, distortion of a wave causes the detection signal not to zero-cross at a data-altering time as shown in FIG. 7. Points A, B, B', C and D in FIG. 3 corresponds to points A, B, B', C and D of the detection signal in FIG. 7. If data is altered at time tB, the detection signal normally zero crosses at point B. In the case that distortion of a waveform makes detection signal zero-cross at point B, the output of the AND gate 13 rises at time tB', instead of tB as shown in FIG. 3.
The detection signal zero-crosses at point D where time tD corresponds to a point where data is altered. If the detection signal includes the point B', where the zero cross is made by the different timing from when data is altered, and the point D, where the zero cross occurs at the timing corresponding to when data is changed, the phase of a reproduced clock signal fluctuates, i.e., a so-called jitter occurs. This bothers stable reception of the signal.
The level compensator shown in FIG. 4 refers to a timing at which the detection signal crosses the reference level VR in order to control the phase of the reproduced clock signal. When the center level of the detection signal coincides with the reference voltage VR as illustrated in FIG. 5, even if the phase of a reproduced clock is shifted, the level compensator acquires a phase difference .theta. between time ti when the detection signal crosses the reference voltage VR and time tj when the reproduced clock is changed, and controls the phase of the reproduced clock.
In the case that the detection signal somehow has its center frequency level shifted from the reference voltage VR, the following shortcoming would occur. If the center level of the detection signal is shifted up, points, such as B1 and D, are where the detection signal crosses the reference voltage VR. Even if the reproduced clock is properly synchronized with the detection signal, the phase of the reproduced clock does not coincide with the detected cross points D and B1. The phase of the reproduced clock leads when the cross at the point D is detected, while it lags when the cross at the point B1 is detected. As a result, the reproduced clock will not be synchronized with the detection signal.
Further, if the phase of the reproduced clock is shifted with respect to the detection signal, the reproduced clock cannot be synchronized with the detection signal. When the cross of the signal is detected at the point B, a phase difference .theta. between this cross and the reproduced clock is zero, thus requiring no phase control of the reproduced clock. When the signal crossing at the point D is detected, the phase of the reproduced clock will be erroneously adjusted based on a phase difference .theta.' between this cross and the reproduced clock.
There is another shortcoming in the case of compensating for the center level of the detection signal. The error signal generator 28 determines V(i)-Vs as an augmenter when V(i)&gt;V1. When the GMSK modulation signal is subjected to frequency detection, the resultant detection signal has a level V(i)&gt;V1 at three points A1, A2 and A3. More specifically, augmenters at these points should be V(i)-Vs1, V(i)-Vs2 and V(i)-Vs, respectively. If all the augmenters are determined as V(i)-Vs, however, a compensation difference will occur at the points A1 and A2. The same is true of when V(i)&lt;V2.
The occurrence of the compensation difference described above supposes no phase shift in the reproduced clock signal. If the reproduced clock signal has its phase shifted, A/D conversion will be performed on the level at the point B3, instead of the level at the point A1. The exact augmenter in this case is V(i)-Vs3. When the augmenter is determined as V(i)-Vs or V(i)-Vsl, the phase shift in the reproduced clock signal causes erroneous compensation for the center level of the detection signal, although that level is not actually shifted.